Control of avalanche photodiodes bias voltage

ABSTRACT

An optical communications system using forward error correction (FEC) to correct errors in signals carried by the system. Optical signals on the system are dropped at nodes and converted to electrical signals by avalanche photodiodes (APDs) at the node receivers. An FEC chip operates on the electrical signal to correct errors. The error rate is used to control the APD bias voltage which affects signal noise and therefore error rate. The errors in a predetermined interval are counted and a determination made as to whether the error rate is rising with time. The bias voltage is derived from the value of a counter whose count is incremented each interval. If the error rate is rising, the counting direction is changed.

This invention relates to the control of avalanche photodiodes (APDs).It is particularly concerned with the control of APDs in opticalcommunications circuits.

APDs are widely used in optical communications to convert optical datainto an electrical signal. Fluctuations in the received optical signalare converted into sympathetic fluctuations in the electric signalpassing through the APD device.

In optical communications systems as in any communications system, noiseis a significant factor which affects performance. An optical signalarriving at an APD may have passed through many kilometres of opticalfibre and through several associated optical amplifiers. It will,therefore, have collected noise. In addition to the incoming noisecomponent, the APD itself generates electrical noise which constitutesto the overall noise in the signal output by the APD. The noisegenerated by the APD is superimposed on the electrical currentfluctuations in the device generated by the incoming optical signal.

APDs are biased by a reverse voltage in order to function properly. Thereverse, or bias, voltage is a supply whose negative terminal isconnected to the APD anode and whose positive terminal is connected tothe cathode. The bias causes a small leakage current to flow in thedevice when no light is incident. The current flowing increases withincreasing incident light intensity. It is important for goodperformance of APDs to choose the optimum bias voltage.

Choosing the optimum bias voltage is difficult. It varies betweendevices, not only between manufacturers but also within a particularbatch. Thus, the bias has to be set up accurately when the device isfirst manufactured. Moreover, the optimum bias value varies withtemperature. The bias circuit must therefore monitor local temperatureand adjust the bias voltage accordingly.

To obtain good results over the working temperature range, it isnecessary to set up the temperature coefficient of the correctioncircuit at the time of manufacture.

A further problem arises in that APD characteristics change slightlywith age. This can result in the non-optimum bias voltage being applied.

Some existing APD bias circuits vary the bias voltage in accordance withthe incoming signal strength. However, the improvement in performanceoffered tends to be small.

The problems of bias voltage control are better appreciated byconsidering the nature of photodiodes. In conventional, non-avalanche,photodiodes, incident light photons are absorbed by the light sensitivepart of the device. For each photon absorption, there is a reasonablechance that a nearby electron will receive some or all that energy. If asuitable electron receives sufficient energy, it may free itself fromits silicon atom and become a mobile charge carrier which can travelfrom atom to atom through the crystal structure of the device. Onapplication of an electric field to the device, the charge carrier willtravel towards the positive terminal of the diode where it will beabsorbed, giving up its charge to the external circuit and resulting inan impulse of current. If the photosensitive part of the device isexposed to steady illumination there will be a continuous stream ofcharge carriers and, therefore, an electric current in the externaldevice.

The photosensitivity of the device is created by application of aninternal electric field, requiring a voltage to be applied across thediode terminals. As devices are used to convert incident light intoelectrical current, the voltage bias on the diode must be in thenon-conducting, or reverse, direction so that the current generated isonly due to the incident light.

In avalanche photodiodes, the active region is thin and the bias voltageparticularly high, creating a significantly high electric field strengthwithin the device. Charge carriers produced by incident photonsaccelerate rapidly towards the positive terminal, gaining energy. Ifthey collide with another atom, they may have gained sufficient energyto liberate two or more electrons. Those newly liberated electronsbecome charge carriers and accelerate towards the anode. Each electronmay, in turn, collide with other atoms and liberate two or more furthercarriers thus providing an avalanche of charge carriers and amplifyingthe effect of the incident photon.

The number of charge carriers liberated by a photon is referred to asthe gain M of the APD. If one considers a photon which liberates asingle carrier, that carrier accelerates and liberates two furthercarriers. Each of those accelerate and liberate two further carriers,making a total of four. If there are 10 such collisions before reachingthe anode, 1024 electrons will give off their charge to the externalcircuit and so the APD gain, or multiplication factor exhibited is 1024.

The gain is dependent on both the bias voltage and temperature and ishighly non-linear as can be seen from FIG. 1 which plots gain againstbias voltage for a device operated at three temperatures, 25° C., 50° C.and 75° C. The gain axis is logarithmic.

It will be appreciated that the avalanche process described isstatistical in nature and gives rise to various high frequency noisesources within the device. Noise generation is particularly sensitive tothe value of M and hence to the bias voltage and temperature.

If one considers a system with a fibre optic transport mechanism such asa fibre-optic cable, an APD device and a low-noise high frequencyamplifier, the amplifier is referred to as a transimpedance amplifier asit converts current fluctuations into a voltage signal. It can be shownthat optimum performance is achieved whenN _(T) =N _(F) +N _(A)

where N_(T) is the noise contribution due to the transimpedanceamplifier, N_(F) is the noise contribution due to the optical fibre andN_(A) is the noise contribution due to the APD device. All the figuresshould refer to the same position in the system, that is the amplifieroutput. N_(T) is constant, N_(f) depends on the incoming optical signaland is therefore outside the control of the optical receiver. Ittherefore follows that optimum performance can only be achieved byadjusting N_(A) which, in turn, is achieved by adjusting the biasvoltage on the APD device.

Bearing in mind the importance of bias control in APD devices, and theproblems and difficulties in achieving optimum control of bias voltagethere is a need for improved APD bias voltage control. The presentinvention aims to address that need and the problems and difficultiesdiscussed above.

The invention resides in the use of measured error rates in the signalto set the bias voltage using a feedback loop.

More specifically there is provided a method of controlling the biasvoltage of an avalanche photodiode in an optical communications systemincluding forward error correction, the method comprising measuring theerror rate in a electrical signal converted from an optical signal bythe avalanche photodiode, and adjusting the bias voltage applied to theavalanche photodiode to minimise the error rate in the electricalsignal.

The invention also provides apparatus for controlling the bias voltageof an avalanche photodiode (APD) in an optical communications systemincluding forward error correction (FEC), comprising an error ratemeasurer for measuring the error rate in an electrical signal convertedfrom an optical signal by the APD, and is an adjustment circuit foradjusting the bias voltage applied to the APD to minimise the measurederror rate.

Embodiments of the invention have the advantage that the APD biasvoltage can be optimised or near optimised under normal operatingconditions. It removes the need to set up the APD voltage accuratelyduring manufacture and removes the need for a highly accurate andtemperature compensated APD voltage supply.

Preferably the error rate is measured over a number of sample periodsand a determination made as whether the error rate is increasing ordecreasing with time. By making this determination over several sampleperiods, short term fluctuations in the error rate do not affect thebias voltage setting.

Preferably the bias voltage is set by the value of a counter which isincremented every sample period. If the error rate is increasing, thecounting direction is changed. In this way, the count tends to theoptimum valve of the bias voltage. The counter is preferably initiallyset to a mid point.

Preferably, the sample interval is variable. This may be in accordancewith the measured error rate whereby the bias voltage is changed rapidlywhen it is a long way from the optimum value and more slowly as itapproaches the optimum value.

A preferred embodiment of invention comprises a pulse counter whichcounts errors detected by the forward error corrector over a timeinterval set by a gating clock. At each new interval, the existing pulsecount is switched to a store and the pulse count starts again. After anumber of counts have been stored, for example 6, decision logicdetermines whether the error rate is increasing or decreasing using analgorithm. An up down counter is set at a mid-point and determines thevalue of the bias voltage. The count is incremented or decremented eachtime interval. If the error rate is determined to be increasing, thecount direction is changed. If the error rate is decreasing the countdirection is unchanged. The output of the counter is converted to ananalog signal by a D to A converter and forms the bias voltage which isapplied to the APD.

Embodiments of the invention will now be described, by way of exampleonly, and with reference to the accompanying drawings in which:

FIG. 1, referred to above, is a graph of gain against bias voltage foran APD operating at three temperatures;

FIG. 2 is a schematic representation of a portion of an opticalcommunications network showing the use of APDs and forward errorcorrection;

FIG. 3 is a block diagram of a system embodying invention; and

FIG. 4 is a flow chart showing how bias voltage can be optimised.

FIG. 2 shows, schematically, the drop side of a node of an opticalnetwork, for example a two fibre 10 GHz optical network which carries a32 channel DWDM (Dense Wave Division Multiplex) signal. The optical DWDMsignal is split from the network by a signal splitter 12 to produce adropped signal output 14. The other output of the splitter is throughtraffic, labelled T, which remains on the network. The dropped signal ispassed to a 32:1 splitter 16 which splits the signal into 32 separatesignals. The remaining circuitry shown applies to one of the outputsonly, although, in practice, it is repeated for each channel.

The output from signal splitter 16 is input to a tuneable filter 20. Thefilter is an essentially mechanical component whose centre frequency iscontrolled by a servo motor.

The output of the filter 18 is a single channel optical signal which isinput to a receiver 22 which includes an APD 23 which converts theoptical signal into an electrical signal which is then output forfurther processing and, eventually, delivered to the end user.

A part of the further processing is error correction. It is well knownin optical communications networks to use forward error correction as ameans of correcting data errors. A degree of redundant coding isintroduced into the data stream according to one of a number of codingalgorithms. One such algorithm is the Reed-Solomon algorithm which is ablock based error correction code which encodes an array of K datasymbols as an input and returns an array of N symbols. Operating in a 10GHz environment, a Reed-Solomon encoder will convert a 9.9 Gbps symbolstream into a 10.7 Gbps stream.

The electrical output from the receiver 22 is passed to a Forward ErrorCorrection (FEC) chip 24 which comprises two main parts. A decoder 26decodes the electrical data symbols and a corrector 28, which operatesunder the control of correction data from the decoder 26, corrects thedecoded data. The corrected data is then output to its intendeddestination.

FEC has the advantage of being transparent to the end user. We haveappreciated that if the error rate in the symbol stream varies, providedthat error rate is not excessive, the errors will be corrected and theend user will be unaware of the fluctuations in the error rate. We havefurther appreciated that changes in the error rate can be monitored tofind the optimum bias voltage for the APD 23.

Thus, in FIG. 2, error pulses 29 from the decoder provide an input to acontrol unit 30 which outputs a signal which, after conversion by adigital-to-analog convertor DAC 32 provides the bias voltage V_(b) tothe avalanche photodiode 23.

FIG. 3 shows the controller 30 of FIG. 2 in more detail. The error pulesreceived from the FEC chip correspond to data errors that have beendetected and will be corrected before being passed on to the end user. Agating clock 34 (not shown in FIG. 2) provides periodic ticks whichdetermine the points in time when the circuiting reevaluates itsinternal calculation.

The error pulses are first counted by a pulse counter 36 between clockticks. At each clock tick, the current counter value is transferred to ahistory store 38. The counter 36 is then reset for the next countinginterval. The store 38 records most recent error counts. The store maybe based on a shift register architecture although other architecturesare possible. On each clock tick it shifts-in the most recent samplefrom the pulse counter and discards the oldest one. Typically, the storewill retain the six most recent samples although other values may beused.

Decision logic 40 is used to determine whether the error count isincreasing or decreasing over time. This may be done in any convenientmanner although one presently preferred method is by an algorithm usingsix consecutive samples and simple Gaussian filters for samples E1, toE6 where E1 is the most recent. The error rate would be increasing, inwhich case the performance is getting worse if:Getting worse: (E ₁+2E ₂ +E ₃)>(E ₄+2E ₅ =E ₆).

The result ‘getting worse’ is a boolean quantity and is true or false (1or 0). At each clock tick, a true value causes a toggle stage 42 tochange state, but a false value causes the toggle to remain unchanged.The toggle stage outputs to an up/down counter 44 which is also clockedby the clock 34 and clocks up or down depending on the value of thetoggle stage. An increasing error rate will therefore cause the counterto change direction at each clock tick, whereas a falling or consistenterror rate will cause it to keep ramping in the same direction.

The current count value is connected by DAC 32 into the analogue biasvoltage V_(b) which in then applied to the APD anode. The counter 33will be set to an initial value which provides the bias voltage and isincremented, up or down, every clock tick in accordance with the togglestate.

The response speed of the control loop is determined by the speed of thegating clock 34 and the size of the up/down counter 44 for a tickinterval to and an N-bit up/down counter, together with an N-bit D/Aconverter 32. It will take 2^(N-1)t seconds to change the APD voltagefrom its mid-point value to an excursion extremity. Thus, an 8 bitcounter and a sample range of 60 ms will take 6.4 seconds to perform theexcursion. The purpose of the loop is to trim accurately a voltage whichdepends on slow-moving or static parameters, so such a long timeconstant is acceptable.

The pulse counter 36 must be chosen to have a size that is large enoughto capture sufficient errors under the worst possible bit error rateconsistent with proper system operation. The system may include an errorrate monitor (not shown) which can identify an excessive error ratecondition.

Initially, the up/down counter is set to its mid point value. Thisallows equal trimming above and below the initial set point. Thisenables a typical working bias voltage to be presented to the APDdevice.

If a fault condition develops, the error rate may increase to a valuewhich is too high to enable the system to obtain a realistic performanceindication. If such a high error rate is detected. The output voltagefrom DAC 32 may be pre-set to the mid-point value. This may be achievedunder the control of the error rate monitor.

Excessive bias or excessive current can damage the sensitive andexpensive APDs and a controller may be used to limit there parameters tosafe working values.

FIG. 4 shows the process described above as a flow chart. At step 100 aninitial bias voltage is set at a typical mid point value. This may beobtained from a look up table. At step 102, the error pulses from theFEC chip are counted by pulse counter 36. At step 104, on the next tick,the contents of the counter are passed to store 38. Steps 102 and 104are continuously repeated. After six counts, the decision logic at 106applies the algorithm described above to determine whether the errorrate is getting worse or not. If it is, the toggle state is changed at108 and the count direction of the up/down counter 44 is changed. Atstep 110, the output of the up/down counter 44 is read, and passed tothe DAC for application as the bias control voltage to the APD.

In the embodiment described, the APD bias voltage is adjusted by asmall, trial, voltage at regular intervals and the FEC error ratemonitored in the previous and current samples. A determination is madeas to whether the error performance is getting better or worse. If it isgetting worse, the polarity of the voltage increment is adjusted.

Embodiments of the invention have the advantage that overall systemperformance can be improved as the APD will always be operated with theoptimum or near-optimum bias voltage regardless of temperature changesor ageing effects. As a consequence, there is no need to set up the APDaccurately during manufacture or to have a highly accurate andtemperature compensated APD bias voltage supply.

The embodiment described may be modified in various ways withoutdeparting from the scope of the invention. For example, a variable tickrate or clock may be used. This has the advantage of speeding up theinitial convergence on the optimum bias voltage whilst improving theresolution, and so the accuracy, when close to the correct optimum biasvoltage. A short tick rate can be used when error counts are high,rapidly pushing the circuit to its final solution. When error rates arelow, the circuit is accurately nudged to its ultimate convergence.Multiple rates may be used.

In one embodiment, clock rates of 10, 20, 40, 80 and 160 ms may be used.If more than 32 errors are constantly encountered in one clock interval,the interval, if not already the lowest, is halved. If less than 8errors are counted in the clock interval, the interval, if not alreadythe highest, is doubled. Other values may, of course, be used.

In a further modification, the up/down counter may be inhibited if noerrors are counted. This prevents a constant hunting around the optimumoperating bias voltage. If error free operation is achieved, the loopwould freeze and error-free operation would be maintained until theexternal conditions change.

Various other modifications are possible and will occur to those skilledin the art without departing from the invention which is limited only bythe following claims.

1. A method of controlling a bias voltage of an avalanche photodiode inan optical communications system including forward error correction, themethod comprising the steps of: a) measuring an error rate in anelectrical signal converted from an optical signal by the avalanchephotodiode over a plurality of sample periods; b) adjusting the biasvoltage applied to the avalanche photodiode to minimize the error ratein the electrical signal by determining whether the error rate isincreasing or decreasing with time; c) determining the bias voltage by avalue of a counter which is incremented or decremented every sampleperiod, and changing a count direction of the counter if the error rateis increasing with time; and d) inhibiting movement of a counter if theerror rate is zero.
 2. The method according to claim 1, and determiningthe sample period by a clock tick of the clock.
 3. The method accordingto claim 2, and varying an interval between clock ticks of the clock. 4.The method according to claim 3, wherein the interval between the clockticks varies in dependence on the measured error rate.
 5. The methodaccording to claim 4, wherein there is a plurality of possible lengthsof the interval, and selecting the interval of increased length if theerror rate is below a first level, and of decreased length if the errorrate is above a second level.
 6. An apparatus for controlling a biasvoltage of an avalanche photodiode (APD) in an optical communicationssystem including forward error correction (FEC), comprising: an errorrate measurer for measuring an error rate in an electrical signalconverted from an optical signal by the APD; and an adjustment circuitfor adjusting the bias voltage applied to the APD to minimize the errorrate, the adjustment circuit comprising decision logic for determiningwhether the error rate is increasing or decreasing with time, and acounter, a counter value of which determines a level of the biasvoltage, and means for changing a count direction of the counter if thedecision logic determines that the error rate is increasing with time,and an inhibitor for inhibiting movement of the counter if the errorrate is zero.
 7. The apparatus according to claim 6, wherein the meansfor changing the count direction is a toggle.
 8. The apparatus accordingto claim 7, comprising a digital to analog converter for converting thecounter value to an analog APD bias voltage.
 9. The apparatus accordingto claim 8, wherein the adjustment circuit comprises an error pulsecounter for counting error pulses over a predetermined interval, and astore for holding error counts for a plurality of earlier intervals. 10.The apparatus according to claim 9, wherein the decision logic operateson the error counts held in the store.
 11. The apparatus according toclaim 10, comprising means for varying the interval over which errorpulses are counted.
 12. The apparatus according to claim 11, wherein theinterval varying means varies the interval in dependence on the errorrate.
 13. The apparatus according to claim 12, wherein the intervalvarying means varies the interval between one of a plurality ofdifferent interval lengths.